1. Field
Exemplary embodiments of the present invention relate to an integrated circuit design, and more particularly, to a data transfer circuit.
2. Description of the Related Art
A non-volatile memory is a data storage in which stored data is retained even when not powered. Data is stored in the non-volatile memory, for example, a flash memory, by using the characteristic that the threshold voltage of a memory cell is changed by controlling the amount of charge retained in a conductive band of a floating gate.
A program pulse is applied to the floating gate, resulting in an increase in the threshold voltage of the memory cell. The threshold voltage of the memory cell is changed using the program pulse according to a value of data to be stored in the memory cell. Threshold voltages of memory cells that store the same data do not have one value, that is, the threshold voltages form a distribution within an uncertain range.
Meanwhile, a plurality of memory cells in the non-volatile memory are electrically coupled to bit lines corresponding to the plurality of memory cells, respectively. The bit lines are electrically coupled to page buffers corresponding to the bit lines, respectively, Each page buffer drives a corresponding bit line at a predetermined voltage level to perform a write operation for a selected memory cell, or detects a voltage of the corresponding bit line to output the detected value to perform a read operation for a selected memory cell. Each page buffer includes one or more latches for storing input data to be driven to a bit line with a predetermined voltage, or the detected data to be output.
Among one or more latches included in the page buffer, a cache latch stores the detected data in the read operation, and drives a data line for transferring data to an exterior according to the stored value. Hereinafter, with reference to FIG. 1, a description will be provided for a process in which data stored in the cache latch of the page buffer is transferred to the exterior.
FIG. 1 is a circuit diagram illustrating a conventional memory,
As illustrated in FIG. 1, the memory includes a plurality of page buffer groups PG0 to PGN, a plurality of local line L0/L0B to LN/LNB, and a global line I0/I0B. Each of the page buffer groups PG0 to PGN includes page buffers PB0 to PBM. Each of the local line L0/L0B to LN/LNB corresponds to the page buffer groups PG0 to PGN, respectively. The global line I0/I0B commonly corresponds to all of the local line L0/L0B to LN/LNB and outputs data transferred from a local line selected among the local line L0/L0B to LN/LNB to an exterior. Each page buffer includes a cache latch LAT.
With reference to FIG. 1, a description will be provided for an operation in which data of a selected page buffer is outputted. Differential data is transferred through positive lines L0 to LN and I0 that transfer positive data and negative lines L0B to LNB and IOB that transfer negative data.
For example, the page buffers PB0 to PBM included in the page buffer group PG0 are electrically coupled to the local line L0/L0B corresponding to the page buffers PB0 to PBM through a plurality of local switches SWB0 to SWBM. Meanwhile, the local line L0/L0B is electrically coupled to the global line I0/I0B through a group switche SWG0 corresponding to the local line L0/L0B. For reference, the page buffers PB0 to PBM included in the respective page buffer group share the corresponding local line pair. Further, the group switches SWG0 to SWGN correspond to the local line L0/L0B to LN/LNB, respectively.
The local switches SWB0 to SWBM are turned-on/off in response to a plurality of column selection signals CS0<0:M> to CSN<0:M>. For example, the local switches SWB0 to SWBM included in the page buffer group PG0 is controlled by the column selection signals CS0<0:M>. The group switches SWG0 to SWGN are turned-on/off in response to a plurality of group selection signals GS<0:N> and GSB<0:N>. For example, the group switch SWG0 is controlled by the of group selection signal GS<0>/GSB<0>. The group selection signals GS<0:N> and GSB<0:N> and the column selection signals CS0<0:M> to CSN<0:M> are selectively activated based on an inputted address (not illustrated in FIG. 1). When a local switch and a group switch corresponding to the activated column selection signal and group selection signal are turned-on, the corresponding cache latch LAT is electrically coupled to the global line I0/I0B. That is, the global line I0/I0B is driven by the cache latch LAT with a voltage corresponding to data stored in the cache latch LAT. For example, in a read operation, when data of the page buffer PB0 within the page buffer group PG0 is outputted, the local switch SWB0 and the group switch SWG0 are turned-on, Thus, the cache latch LAT of the page buffer PB0 within the page buffer group PG0 is electrically coupled to the local line L0/L0B and the global line I0/I0B, and the global line I0/I0B is driven by the cache latch LAT of the pager buffer PB0 within the page buffer group PG0 with a voltage corresponding to the stored data.
Meanwhile, the number of the page buffer groups electrically coupled to one global line I0/I0B and the number of the page buffers included in one page buffer group reach several tens to several hundreds. Therefore, loading of the global line I0/I0B, to be driven, is very large. However, the global line I0/I0B needs to be driven only by the cache latch LAT, specifically, one MOS transistor included in the cache latch LAT, with low drivability.